Amplify Your Career in Physical Design

Master the complete “RTL-to-GDSII” flow. Learn to build and optimize complex chips using industry-standard tools from senior PD leads.
Get 100% placement support to land your dream job at a top-tier company

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Placements

Physical Design Overview

Physical Design (PD) is the process of transforming a logical chip design (RTL code) into a physical layout, the actual “blueprint” for manufacturing. This is where the digital world meets the laws of physics.

As a PD engineer, you will solve the complex puzzle of arranging millions of components to meet strict targets for PPA (Power, Performance, and Area). With chips becoming faster and more complex, the demand for skilled PD engineers who can successfully “tape out” a design is higher than ever. At Tri-Amp, we train you to be a job-ready PD expert from day one.

Duration

24 Weeks / 6 Months

TRAINING MODES

Full-Time Offline (Classroom) & Live Online

DESIGNED FOR

B.Tech/M.Tech Graduates & Working Professionals in VLSI

  • Flexible Learning: Choose between immersive Offline (Classroom) training at our state-of-the-art lab or interactive Live Online classes.
  • Hands-On Labs: The course is 70% practical. You will have 24/7 remote access to our servers to work on projects using licensed EDA tools.
  • Dedicated Support: Get your doubts cleared instantly through dedicated support channels and scheduled 1-on-1 mentorship sessions with your trainers.
  • Total Duration: 24 Weeks (6 Months)
  • Class Schedule:
    Offline/Online: 5 days a week (Mon-Fri)
    Daily Sessions: 3 hours of expert-led theory + 4 hours of dedicated, mentored lab sessions.
  • Total Hours: 400+ hours of intensive, hands-on learning.

  • PD Tools: Synopsys ICC2, Cadence Innovus

  • Synthesis: Synopsys Design Compiler (DC)

  • Signoff (STA): Synopsys PrimeTime (PT)

  • Signoff (PV): Siemens Calibre (for DRC/LVS)

  • Lab Access: 24/7 remote VPN access to our high-performance servers, ensuring you work on licensed, full-version tools on advanced technology nodes (e.g., 16nm/7nm).

  • Fresh Graduates: B.E/B.Tech/M.E/M.Tech in ECE, EEE, or allied fields (e.g., 2023/2024/2025 pass-outs).

  • Working Professionals: Engineers in testing, validation, or other domains looking to transition into a core VLSI career.

  • Faculty: College lecturers seeking to upgrade their skills with current industry practices.

  • Prerequisites: Strong fundamentals in Digital Logic Design. Basic knowledge of Verilog is highly recommended.

  • Flexible Payments: Pay the course fee through secure online banking, credit/debit cards, or UPI.

  • EMI Options: We offer no-cost EMI options through our financial partners. Talk to our admissions counselor to find a payment plan that works for you.

  • Our Commitment: Our dedicated placement team provides 100% placement support as a core part of the program.

  • Career Prep: We conduct rigorous mock interviews, technical presentation sessions, and resume-building workshops.

  • Hiring Partner Network: We have direct connections with top-tier semiconductor companies and will actively schedule your interviews for open positions.

Tri-Amp’s Physical Design Curriculum

1: Essentials of Linux
  • Introduction to Linux,
  • Command Line Operators,
  • File Operations, Processes,
  • Text Editors,
  • Text Manipulating,
  • Network Operations,
  • Special Keystrokes
  • GVIM
2: Digital Design
  • Number System, Boolean Algebra,
  • SOP and POS, K-Map,
  • Combinational circuits, Sequential circuits,
  • Finite State machines,
  • Frequency Division,
  • Setup and Hold time checks,
  • Advance Design Issues: Metastability, Noise Margins Power,
  • Fanout, Timing Considerations, FIFO Depth Calculation
3: CMOS Devices and Technology
  • Electronic Devices, Power Sources, Thevenin and Norton Theorem
  • Semiconductors Device Physics : Atomic Structure, Electronic Configuration, Doping, Diode – Biasing and VI Characteristics
  • MOSFET : Regions of operation, VI Characteristics
  • Function implementation using CMOS
  • Stick Diagram and Layout
  • Second order effects : Body Effect, Channel length modulation, Punch through, subthreshold conduction, DIBL
  • Process Technology : Clean Room, Wafer manufacturing, Oxidation, Diffusion, Ion Implementation, Lithography
4: Verilog HDL
  • Introduction to Verilog
  • Overview of Digital design with Verilog HDL
  • Hierarchical Modeling Concepts: Top-down, bottom-up Design Methodology, modules, components of simulation, stimulus block.
  • Modeling Styles in Verilog: Behavioral or algorithmic level, data flow level, gate level, switch level.
  • Basic concepts: Lexical conventions, Operators, data types, System tasks, directives, File Input and output.
  • Modules and Ports: Module definition, port declaration, connecting ports, hierarchical referencing.
  • Behavioral Modeling: Initial and always, blocking and non blocking statements, delay control, event control, conditional statements, loops, sequential and parallel blocks.
5: Synthesis
  • ASIC Design flow and role of Synthesis
  • Synthesis flow
  • Writing timing constraints in SDC format
  • Constraining the design for timing, power, area goals, set optimization techniques.
  • Synthesize the design.
  • Generate and analyze the reports, save the netlist and SDC.
6: Logic Equivalence Checking (LEC)
  • Formal Verification
  • Understanding & Matching compare points
  • Debugging non equivalent points
  • What-If Analysis
7 : TCL Scripting
  • Features of TCL and Applications.
  • TCL commands, Variables, arithmetic expressions, comments, identifiers, reserved words, data types, decisions, loops, arrays, strings, file I/O and procedures.
  • Scripting exercises from simple problems to complex problems, in an incremental manner and using tools like Prime Time, ICC2.
8: Introduction to Physical Design, Data Preparation and Sanity Checks
  • Introduction to physical design and Physical Design Flow, Data preparation : Files required for PD ( Netlist, SDC, Libraries, Technology files, TLU+), the contents of each input file.
9: Floorplan
  • Sanity Checks
  • Goals of Floorplanning
  • Different aspects of floorplanning
  • Rectangle/Rectilinear floorplans
  • Die size estimation (Core Utilization, Aspect ratio)
  • IO placement
  • Macro placement and guidelines
  • Channel-spacing estimation
10: Power Routing
  • Goals of Power Routing
  • Power distribution structure (Rings, straps and follow-pin/std cell rail)
  • Metal stack information
  • Power planning methodology
  • IR drop analysis, types of power consumption
  • Why Low power and low power techniques. Electro-migration analysis
11: Placement
  • Goals of Placement, types of placements
  • Pre-place (End-cap, Tap & I/O Buffer) cells
  • Placement optimization
  • Congestion analysis
  • Timing analysis
  • Tie-cells
  • High-Fanout Net Synthesis
  • Scan chain re-ordering
  • Path Grouping and creating Bounds
12: Timing Analysis (Pre Layout STA) & Optimization
  • STA Overview and concepts
  • Basic timing checks (setup, hold)
  • Understanding timing constraints (SDC)
  • Timing corners
  • Timing report analysis
  • General optimization techniques
  • Typical causes for timing violations and strategies for fixing the same
  • Pre-CTS optimization to Fix setup violations.
13: Clock Tree Synthesis (CTS)
  • Goals of CTS, Clock tree Methodologies
  • Constraints for CTS
  • Building clock tree
  • Analyze the results
  • Post-CTS optimization : Fixing Setup and Hold violations.
14: Routing
  • Goals of Routing
  • Stages of Routing: Global Routing, Track assignment and Detail Routing
  • Routing options
  • Fixing of routing violations (DRC, LVS)
  • Post route optimization
  • Issues in routing and guidelines for optimum routing results.
15: Post Layout STA
  • Post layout STA using SPEF
  • Multi Mode Multi Corner STA
  • Derating factors
  • PVT, OCV Variations
  • Crosstalk Analysis
16: ECO Flow
  • What is ECO
  • Types of ECO
  • Timing & Functional ECO
  • Performing the ECO placement and routing.
17: Sign-off Checks
  • Physical Verification (DRC, LVS),
  • IR drop analysis,
  • Electro-Migration Analysis
Projects

Projects will be given converging Netlist to GDSII flow. Various projects that will allow the students to understand the intricacies of implementation for minimum area, low power, high performance. The method of execution will be similar to typical block level Physical Design work/project in the industry. Block level input database will be given and the participant has to deliver GDS II, after cleaning all the issues during sign-off checks.

1: Essentials of Linux
  • Introduction to Linux,
  • Command Line Operators,
  • File Operations, Processes,
  • Text Editors,
  • Text Manipulating,
  • Network Operations,
  • Special Keystrokes
  • GVIM
2: Digital Design
  • Number System, Boolean Algebra,
  • SOP and POS, K-Map,
  • Combinational circuits, Sequential circuits,
  • Finite State machines,
  • Frequency Division,
  • Setup and Hold time checks,
  • Advance Design Issues: Metastability, Noise Margins Power,
  • Fanout, Timing Considerations, FIFO Depth Calculation
3: CMOS Devices and Technology
  • Electronic Devices, Power Sources, Thevenin and Norton Theorem
  • Semiconductors Device Physics : Atomic Structure, Electronic Configuration, Doping, Diode – Biasing and VI Characteristics
  • MOSFET : Regions of operation, VI Characteristics
  • Function implementation using CMOS
  • Stick Diagram and Layout
  • Second order effects : Body Effect, Channel length modulation, Punch through, subthreshold conduction, DIBL
  • Process Technology : Clean Room, Wafer manufacturing, Oxidation, Diffusion, Ion Implementation, Lithography
4: Verilog HDL
  • Introduction to Verilog
  • Overview of Digital design with Verilog HDL
  • Hierarchical Modeling Concepts: Top-down, bottom-up Design Methodology, modules, components of simulation, stimulus block.
  • Modeling Styles in Verilog: Behavioral or algorithmic level, data flow level, gate level, switch level.
  • Basic concepts: Lexical conventions, Operators, data types, System tasks, directives, File Input and output.
  • Modules and Ports: Module definition, port declaration, connecting ports, hierarchical referencing.
  • Behavioral Modeling: Initial and always, blocking and non blocking statements, delay control, event control, conditional statements, loops, sequential and parallel blocks.
5: Synthesis
  • ASIC Design flow and role of Synthesis
  • Synthesis flow
  • Writing timing constraints in SDC format
  • Constraining the design for timing, power, area goals, set optimization techniques.
  • Synthesize the design.
  • Generate and analyze the reports, save the netlist and SDC.
6: Logic Equivalence Checking (LEC)
  • Formal Verification
  • Understanding & Matching compare points
  • Debugging non equivalent points
  • What-If Analysis
7 : TCL Scripting
  • Features of TCL and Applications.
  • TCL commands, Variables, arithmetic expressions, comments, identifiers, reserved words, data types, decisions, loops, arrays, strings, file I/O and procedures.
  • Scripting exercises from simple problems to complex problems, in an incremental manner and using tools like Prime Time, ICC2.
8: Introduction to Physical Design, Data Preparation and Sanity Checks
  • Introduction to physical design and Physical Design Flow, Data preparation : Files required for PD ( Netlist, SDC, Libraries, Technology files, TLU+), the contents of each input file.
9: Floorplan
  • Sanity Checks
  • Goals of Floorplanning
  • Different aspects of floorplanning
  • Rectangle/Rectilinear floorplans
  • Die size estimation (Core Utilization, Aspect ratio)
  • IO placement
  • Macro placement and guidelines
  • Channel-spacing estimation
10: Power Routing
  • Goals of Power Routing
  • Power distribution structure (Rings, straps and follow-pin/std cell rail)
  • Metal stack information
  • Power planning methodology
  • IR drop analysis, types of power consumption
  • Why Low power and low power techniques. Electro-migration analysis
11: Placement
  • Goals of Placement, types of placements
  • Pre-place (End-cap, Tap & I/O Buffer) cells
  • Placement optimization
  • Congestion analysis
  • Timing analysis
  • Tie-cells
  • High-Fanout Net Synthesis
  • Scan chain re-ordering
  • Path Grouping and creating Bounds
12: Timing Analysis (Pre Layout STA) & Optimization
  • STA Overview and concepts
  • Basic timing checks (setup, hold)
  • Understanding timing constraints (SDC)
  • Timing corners
  • Timing report analysis
  • General optimization techniques
  • Typical causes for timing violations and strategies for fixing the same
  • Pre-CTS optimization to Fix setup violations.
13: Clock Tree Synthesis (CTS)
  • Goals of CTS, Clock tree Methodologies
  • Constraints for CTS
  • Building clock tree
  • Analyze the results
  • Post-CTS optimization : Fixing Setup and Hold violations.
14: Routing
  • Goals of Routing
  • Stages of Routing: Global Routing, Track assignment and Detail Routing
  • Routing options
  • Fixing of routing violations (DRC, LVS)
  • Post route optimization
  • Issues in routing and guidelines for optimum routing results.
15: Post Layout STA
  • Post layout STA using SPEF
  • Multi Mode Multi Corner STA
  • Derating factors
  • PVT, OCV Variations
  • Crosstalk Analysis
16: ECO Flow
  • What is ECO
  • Types of ECO
  • Timing & Functional ECO
  • Performing the ECO placement and routing.
17: Sign-off Checks
  • Physical Verification (DRC, LVS),
  • IR drop analysis,
  • Electro-Migration Analysis
Projects

Projects will be given converging Netlist to GDSII flow. Various projects that will allow the students to understand the intricacies of implementation for minimum area, low power, high performance. The method of execution will be similar to typical block level Physical Design work/project in the industry. Block level input database will be given and the participant has to deliver GDS II, after cleaning all the issues during sign-off checks.

What Makes Tri-Amp Stand Out

We’re committed to providing an unparalleled learning and career experience.

Flexible Learning Modes

Choose the learning environment that suits you best. We offer comprehensive full-time courses with both offline (classroom) and live online modes.

Expert Trainers & 1-on-1 Mentorship

Learn directly from industry architects with 20+ years of experience, who provide 1-on-1 mentorship, personalized feedback, and direct career guidance.

Real-World Internship Programs

Bridge the gap between theory and practice with our short-term and long-term internship programs, giving you invaluable industry exposure on real projects.

Job-Ready Interactive Sessions

Master the skills employers want. We conduct rigorous mock interviews and technical presentations to sharpen your domain expertise and placement readiness.

Full Access to Licensed EDA Tools

Gain practical proficiency using licensed, industry-standard EDA tools from Cadence, Synopsys, and Siemens. You will work on the real thing, not simulations.

100% Placement Support

Your success is our mission. We provide 100% placement support, from resume optimization to direct connections with our extensive network of hiring partners.

Ready to Master the Full PD Flow?

You’ve seen the expert-led curriculum. The next step is to build your personal career path.

This form helps us understand your goals. When you tell us your qualification, your chosen domain, and your preferred learning mode, you’re not just signing up for a list.

You are enabling our expert industry counselors to:

  • Review Your Profile: We will personally review your background to confirm your eligibility and find the best fit.

  • Provide a Custom Roadmap: We’ll contact you to discuss the exact path from your current qualifications to a top-tier VLSI job.

  • Match You with an Expert: We’ll ensure you get to speak with the right person who understands your chosen domain.

This is a free, no-pressure career consultation with a VLSI professional. Let’s get started.

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